Receivers that receive data transmitted over high-speed serial links typically latch the incoming data using a slicer circuit that is driven by a clock running at either the full rate or half the rate of the incoming data stream. The latched data is then de-multiplexed in a de-multiplexer circuit that is driven by a clock running at a sub-multiple of the latching frequency. Typically, the same clock generating circuitry is used to generate both the latching and de-multiplexing clock signals, and these signals must be amplified to drive the substantial capacitive loads within the receiver. Typically, shunt-peaked amplifiers are used for this purpose.
FIG. 1 is a schematic illustration of a conventional clock distribution scheme using shunt-peaked amplifiers to distribute the clock signals needed by a receiver using a high speed de-multiplexer. As shown in FIG. 1, a frequency programmable receiver 100 receives a data stream 101. The data stream 101 is clocked into a slicer 130, consisting of flip-flops 131 and 132, using a clock signal 102b. In the full-rate clocked slicer 130 shown in FIG. 1, the period T of clock signal 102b matches the duration of bits in data stream 101. Clock signal 102b is derived from a clock signal 102 that is generated by a phase-locked loop (PLL) 110. The clock signal 102 output from PLL 110 is amplified by a shunt-peaked amplifier 120 to produce a clock signal 102b having sufficient amplitude to drive the capacitive load 105 of slicer 130. Slicer 130 produces an output data stream 101b that is subsequently de-multiplexed by a 1-2 de-multiplexer 170 at half the rate of data stream 101. De-multiplexer 170 consists of a first pair of latches 140/142 and a second group of latches 150/152/154 that latch every other bit in data stream 101b. That is, latches 140/142 latch the even bits in data stream 101b, while latches 150/152/154 latch the odd bits in data stream 101b. The latches 140/142 and 150/152/154 are driven by a clock signal 104b having a period 2T that is twice the period of clock signal 102b. Clock signal 104b is also derived from the clock signal 102 output by PLL 110 by a pair of latches 112/114 that divide clock signal 102 into a clock signal 104 that has twice the period of clock signal 102. Clock signal 104 is then amplified by a shunt-peaked amplifier 122 to produce clock signal 104b having sufficient amplitude to drive the capacitive load 106 presented by 1:2 de-multiplexer 170.
A significant draw-back to the clock distribution scheme shown in FIG. 1 is that shunt peaked amplifiers 120 and 122 consume significant power, especially when compared to other types of amplifiers such as resonant amplifiers. Despite this draw back, frequency programmable receivers such as receiver 100 are designed with shunt peaked amplifiers 120 and 122 rather than energy efficient resonant clock amplifiers because resonant clock amplifiers introduce frequency dependent time delays. These delays result in data synchronization issues whenever the frequency of the receiver 100 is changed.
As shown in FIG. 1, the frequency of receiver 100 can be programmed via one or more digital inputs 108 that allow the clock 102 generated by PLL 110 to have one of several programmable frequencies. When a new frequency for clock 102 is selected, a calibration block 160 (which can be internal or external to PLL 110), tunes a clock generation element within PLL 110 to generate clock 102 at the new frequency. For example, PLL 110 can include a tunable voltage controlled oscillator or VCO (not shown), such as an LC-tank VCO. Calibration block 160 can include a look-up table 180, indexed by the digital inputs 108, that stores one or more control words that can be output on control lines 161 through 165 to select the frequency of clock signal 102. For example, the control words can be used to change the capacitance of the LC-tank based VCO within PLL 110, thereby changing the oscillation frequency of the VCO and the clock signal 102 that is produced by PLL 110.
Frequency programmable receiver 100 also includes a clock and data recovery (CDR) circuit 190. Like the calibration block 160, CDR circuit 190 can be internal or external to PLL 110. In operation, CDR circuit 190 adjusts the phase of clock signal 102 so that amplified clock signal 102b is centered on the bit windows of data stream 101 at slicer 130. This ensures the correct latching of data bits in data stream 101 at slicer 130. By design, when receiver 100 is programmed to operate at its highest programmable frequency and CDR circuit 190 has centered amplified clock signal 102b on the bit windows of data stream 101 at slicer 130, amplified clock signal 104b is also centered on the bit windows of latched data stream 101b at de-multiplexer 170. When receiver 100 is programmed to operate at a lower frequency, CDR circuit 190 will generally re-adjust the phase of clock signal 102 to ensure that amplified clock signal 102b remains centered on the bit windows of data stream 101 at slicer 130. However, this re-adjustment can cause the misalignment of amplified clock signal 104b with respect to the bit windows of data stream 101b at de-multiplexer 170. To prevent this, the clock amplifiers 120 and 122, slicer 130, and latches 112/114 in receiver 100 are designed so that they introduce approximately equal delays into the clock signals 102b and 104b over the programmable frequency range of receiver 100. Since clock amplifier 120 amplifies a clock signal 102 that is twice the frequency of the clock signal 104 that is amplified by clock amplifier 122, this generally requires that the delays introduced by clock amplifiers 120 and 122 be essentially frequency independent over the programmable frequency range of receiver 100. While shunt-peaked amplifiers introduce such frequency independent delays, resonant clock amplifiers do not. Consequently, receiver 100 is designed to use shunt peaked amplifiers, despite the power savings that can be achieved using resonant clock amplifiers.